A compact size and big picture screen have become a mainstream development of displays; thus, a demand for the display with a narrow bezel is increased. However, with the growth of a resolution of the displays, an amount of scan lines and data lines which are positioned outside a display area also increases. Therefore, under the situation of the narrower bezel as well as increasing circuit traces in the display, how to design the traces within the narrow space has become a different problem for manufacturers.
Moreover, due to a resolution limit of exposure machines, the minimal spacing between lines has a certain limit; thus, all the traces can not be arranged on an identical layer. Therefore, a dual trace on two respective layers has been proposed. Referring to FIG. 1, FIG. 1 depicts a schematic drawing illustrating a display with the dual trace in the prior. There are a plurality of traces 20 positioned around an active area 12 of a liquid crystal substrate 10; the traces 20 establish a coupling between a driver chip 14 and active devices within the active area 12. The traces 20 may include data lines and scan lines. Whether the data lines or the scan lines, the so-called dual trace means that any two adjacent traces 20 are respectively located at different layers, as shown in an enlarged, partial cross-sectional view on the right side of FIG. 1. By this design, the two adjacent traces 20 can be extremely close; as a result, the space around the active area 12 can be reduced, thereby achieving the demand for the narrow bezel products.
However, because a thickness of a protective layer 25 covering the traces 20 that is positioned at an upper layer 25 is thinner, the protective layer 25 is broken easily, to cause a broken line. In addition, as shown in FIG. 1, because the two adjacent traces 20 are extremely close, it may cause a poor coating ability for the protective layer 25, resulting in a crack easily. That is also easy to make the protective layer 25 break, and similarly causes that the trace 20 at the upper layer is broken.
Moreover, although materials and process parameters for fabricating the traces 20 on the upper and lower layers are the same, the traces 20 on the upper and lower layers may have different line widths due to a variation in the manufacture processes because the upper and lower traces 20 are formed on the different layers. This makes the traces 20 on the upper and lower layers have different resistances, and it may cause a striped defect on a display image.
Accordingly, there is a need to improve the conventional technology, so as to overcome the drawbacks of the broken lines existed in the dual trace and the striped defect formed on the display image in the prior art.